1. Field
Example embodiments relate to semiconductor devices and methods of forming the same. Other example embodiments relate to void boundary structures, semiconductor devices having the void boundary structures and methods of forming the same.
2. Description of the Related Art
A semiconductor device is manufactured to have highly integrated semiconductor interconnections disposed on a semiconductor substrate corresponding to reduction of a design rule. The design rule determines a pitch of the semiconductor interconnections in a given semiconductor manufacturing process. The reduction of the design rule enables width and spacing of the semiconductor interconnections to be made significantly smaller than allowable parameters for a given semiconductor manufacturing process. The semiconductor interconnections may be made to occupy a relatively small space in a semiconductor device so as to achieve increased integration of the semiconductor device.
The semiconductor interconnections, which have the pitch smaller than the allowable parameters of the given semiconductor manufacturing process, may have undesirable current transmission capability. The reduction of the design rule may increase inner resistance of the semiconductor interconnections and parasitic capacitance between the semiconductor interconnections, thereby inhibiting flow of current. As a result, a semiconductor device may be highly integrated using the semiconductor interconnections with the reduction of the design rule, but it may not have an increased operating speed.
A semiconductor device with inner resistance of interconnections, or parasitic capacitance between the interconnections being reduced in spite of a reduced design rule is disclosed in the conventional art. According to the conventional art, a first insulating layer may be disposed on a semiconductor substrate. Copper interconnections may be disposed on the first insulating layer. A second insulating layer may be formed on the first insulating layer to cover the copper interconnections and form voids between them, and then a third insulating layer may be disposed on the second insulating layer.
However, the conventional art allows the current transmission capability of the copper interconnections to remain at the same level as before reduction of a design rule, or may be incapable of enhancing the current transmission capability of the copper interconnections to the higher level as before the reduction of the design rule. The voids between the copper interconnections may be only formed parallel to the top surface of the semiconductor substrate. When the voids between the copper interconnections are unstably formed, they may be filled with the third insulating layer.